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C8051F380/1/2/3/4/5/6/7/C
27.1. PCA Counter/Timer
The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte
(MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches
the value of PCA0H into a “snapshot” register; the following PCA0H read accesses this “snapshot” register.
Reading the PCA0L register first guarantees an accurate reading of the entire 16-bit PCA0 counter.
Reading PCA0H or PCA0L does not disturb the counter operation. The CPS2 – CPS0 bits in the PCA0MD
register select the timebase for the counter/timer as shown in Table 27.1.
When the counter/timer overflows from 0xFFFF to 0x0000, the Counter Overflow Flag (CF) in PCA0MD is
set to logic 1 and an interrupt request is generated if CF interrupts are enabled. Setting the ECF bit in
PCA0MD to logic 1 enables the CF flag to generate an interrupt request. The CF bit is not automatically
cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by soft-
ware. Clearing the CIDL bit in the PCA0MD register allows the PCA to continue normal operation while the
CPU is in Idle mode.
Table 27.1. PCA Timebase Input Options
CPS2
0
0
0
0
1
1
1
CPS1
0
0
1
1
0
0
1
CPS0
0
1
0
1
0
1
x
Timebase
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock divided
by 4)
System clock
External oscillator source divided by 8 *
Reserved
Note: External oscillator source divided by 8 is synchronized with the system clock.
IDLE
PCA0MD
PCA0CN
C W W
I D D
D T L
C C C E
P P P C
S S S F
C C
F R
C C C C C
C C C C C
F F F F F
L E C
K
2 1 0
4 3 2 1 0
PCA0L
read
To SFR Bus
Snapshot
Register
SYSCLK/12
SYSCLK/4
000
001
Timer 0 Overflow
ECI
010
011
0
1
PCA0H
PCA0L
Overflow
To PCA Interrupt System
SYSCLK
External Clock/8
100
101
CF
To PCA Modules
Figure 27.2. PCA Counter/Timer Block Diagram
Rev. 1.4
299
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